Dr. Pourus Mehta – Scientist at Bhabha Atomic Research Centre

Dr. Pourus Mehta received his Ph.D. degree in Physics from University of Mumbai through research conducted at Bhabha Atomic Research Centre and Indian pourusInstitute of Technology – Bombay in year 2007. His doctoral thesis was centered on the development of Silicon Drift Detectors (Proto-type & Commercial grade) for X-ray spectroscopy applications. He subsequently joined Indian Institute of Technology – Bombay as Sr. Research Engineer where he conducted research on Diamond based Alpha Particle detectors. In year 2008, he received a Post-Doctoral fellowship from Tata Institute of Fundamental Research – Mumbai for conducting research on Silicon Photo-multiplier devices. In the same year, he was selected for a permanent position as Scientist with the Bhabha Atomic Research Centre. He has been a member of the India-CMS Collaboration and contributed to the discovery of the Higg’s Boson (Nobel Prize in Physics 2013) at the CMS detector at CERN, Geneva in year 2010. He is a reviewer for various peer reviewed international research journals like the Global Journals Inc. (U.S.A.), International Journal of Physics (U.S.A.) etc. He has the distinction of having authored more than 120 international papers (personal & collaboration) together with 9 conference publications and a book. His interests dwell in the fields of Semiconductor Device Physics and Technology, Bio-medical electronics, Integrated Circuit design & Embedded Systems design. He has more than 12 years of active research experience and has been a member of various scientific societies (IEEE-Mumbai chapter, IOP-UK, etc.).

Apart from his scientific endeavors, he is also a fervent admirer of art and culture and has written more than 140 poems in English, Hindi & Urdu languages.

His recent book on A Treatise on the Development of the Silicon Drift Detector gives a glimpse into the various stages involved in the development of a Silicon Drift Detector (SDD) with on-chip JFET. The development of the SDD was carried out in phased manner, with the proto-type development being carried out at the Indian Institute of Technology-Bombay (IIT-B) followed by development of commercial grade SDDs at Bharat Electronics Ltd., Bangalore (BEL). Simulations in TCAD (device and process) were employed to arrive at optimized parameter values for the SDD with on-chip JFET. Various different kinds of SDDs and JFETs were designed to study the effect of a variation in design parameters on the performance parameters. The fabrication process for proto-type SDD was formulated for achieving a high breakdown voltage (>100V) coupled with a low leakage current achievable at IIT-B. Further, designs of the SDD with on-chip JFET were generated for fabrication at BEL. Fabrication of both SDD and JFET over high resistivity Silicon posed a significant technological challenge mitigated by process optimization in TCAD. Click Here to buy the book online.

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